

module axi_crossbar_wapper (
    // input wire              clk,
    // input wire              rst_n,
    Axi4LiteIf.slave        slave,
    Axi4LiteIf.master       masters[8]
);

axi_crossbar axi_devices_crossbar_inst (
  .aclk                     (slave.clk),                    // input wire aclk
  .aresetn                  (slave.rst_n),              // input wire aresetn
  .s_axi_awaddr             (slave.awaddr),    // input wire [31 : 0] s_axi_awaddr
  .s_axi_awprot             (slave.awprot),    // input wire [2 : 0] s_axi_awprot
  .s_axi_awvalid            (slave.awvalid),  // input wire [0 : 0] s_axi_awvalid
  .s_axi_awready            (slave.awready),  // output wire [0 : 0] s_axi_awready
  .s_axi_wdata              (slave.wdata),      // input wire [31 : 0] s_axi_wdata
  .s_axi_wstrb              (slave.wstrb),      // input wire [3 : 0] s_axi_wstrb
  .s_axi_wvalid             (slave.wvalid),    // input wire [0 : 0] s_axi_wvalid
  .s_axi_wready             (slave.wready),    // output wire [0 : 0] s_axi_wready
  .s_axi_bresp              (slave.bresp),      // output wire [1 : 0] s_axi_bresp
  .s_axi_bvalid             (slave.bvalid),    // output wire [0 : 0] s_axi_bvalid
  .s_axi_bready             (slave.bready),    // input wire [0 : 0] s_axi_bready
  .s_axi_araddr             (slave.araddr),    // input wire [31 : 0] s_axi_araddr
  .s_axi_arprot             (slave.arprot),    // input wire [2 : 0] s_axi_arprot
  .s_axi_arvalid            (slave.arvalid),  // input wire [0 : 0] s_axi_arvalid
  .s_axi_arready            (slave.arready),  // output wire [0 : 0] s_axi_arready
  .s_axi_rdata              (slave.rdata),      // output wire [31 : 0] s_axi_rdata
  .s_axi_rresp              (slave.rresp),      // output wire [1 : 0] s_axi_rresp
  .s_axi_rvalid             (slave.rvalid),    // output wire [0 : 0] s_axi_rvalid
  .s_axi_rready             (slave.rready),    // input wire [0 : 0] s_axi_rready
  .m_axi_awaddr             ({masters[7].awaddr  , masters[6].awaddr  ,masters[5].awaddr ,masters[4].awaddr  , masters[3].awaddr  ,masters[2].awaddr  , masters[1].awaddr  ,masters[0].awaddr }),    // output wire [95 : 0] m_axi_awaddr
  .m_axi_awprot             ({masters[7].awprot  , masters[6].awprot  ,masters[5].awprot ,masters[4].awprot  , masters[3].awprot  ,masters[2].awprot  , masters[1].awprot  ,masters[0].awprot }),    // output wire [8 : 0] m_axi_awprot
  .m_axi_awvalid            ({masters[7].awvalid , masters[6].awvalid ,masters[5].awvalid,masters[4].awvalid , masters[3].awvalid ,masters[2].awvalid , masters[1].awvalid ,masters[0].awvalid}),  // output wire [2 : 0] m_axi_awvalid
  .m_axi_awready            ({masters[7].awready , masters[6].awready ,masters[5].awready,masters[4].awready , masters[3].awready ,masters[2].awready , masters[1].awready ,masters[0].awready}),  // input wire [2 : 0] m_axi_awready
  .m_axi_wdata              ({masters[7].wdata   , masters[6].wdata   ,masters[5].wdata  ,masters[4].wdata   , masters[3].wdata   ,masters[2].wdata   , masters[1].wdata   ,masters[0].wdata  }),      // output wire [95 : 0] m_axi_wdata
  .m_axi_wstrb              ({masters[7].wstrb   , masters[6].wstrb   ,masters[5].wstrb  ,masters[4].wstrb   , masters[3].wstrb   ,masters[2].wstrb   , masters[1].wstrb   ,masters[0].wstrb  }),      // output wire [11 : 0] m_axi_wstrb
  .m_axi_wvalid             ({masters[7].wvalid  , masters[6].wvalid  ,masters[5].wvalid ,masters[4].wvalid  , masters[3].wvalid  ,masters[2].wvalid  , masters[1].wvalid  ,masters[0].wvalid }),    // output wire [2 : 0] m_axi_wvalid
  .m_axi_wready             ({masters[7].wready  , masters[6].wready  ,masters[5].wready ,masters[4].wready  , masters[3].wready  ,masters[2].wready  , masters[1].wready  ,masters[0].wready }),    // input wire [2 : 0] m_axi_wready
  .m_axi_bresp              ({masters[7].bresp   , masters[6].bresp   ,masters[5].bresp  ,masters[4].bresp   , masters[3].bresp   ,masters[2].bresp   , masters[1].bresp   ,masters[0].bresp  }),      // input wire [5 : 0] m_axi_bresp
  .m_axi_bvalid             ({masters[7].bvalid  , masters[6].bvalid  ,masters[5].bvalid ,masters[4].bvalid  , masters[3].bvalid  ,masters[2].bvalid  , masters[1].bvalid  ,masters[0].bvalid }),    // input wire [2 : 0] m_axi_bvalid
  .m_axi_bready             ({masters[7].bready  , masters[6].bready  ,masters[5].bready ,masters[4].bready  , masters[3].bready  ,masters[2].bready  , masters[1].bready  ,masters[0].bready }),    // output wire [2 : 0] m_axi_bready
  .m_axi_araddr             ({masters[7].araddr  , masters[6].araddr  ,masters[5].araddr ,masters[4].araddr  , masters[3].araddr  ,masters[2].araddr  , masters[1].araddr  ,masters[0].araddr }),    // output wire [95 : 0] m_axi_araddr
  .m_axi_arprot             ({masters[7].arprot  , masters[6].arprot  ,masters[5].arprot ,masters[4].arprot  , masters[3].arprot  ,masters[2].arprot  , masters[1].arprot  ,masters[0].arprot }),    // output wire [8 : 0] m_axi_arprot
  .m_axi_arvalid            ({masters[7].arvalid , masters[6].arvalid ,masters[5].arvalid,masters[4].arvalid , masters[3].arvalid ,masters[2].arvalid , masters[1].arvalid ,masters[0].arvalid}),  // output wire [2 : 0] m_axi_arvalid
  .m_axi_arready            ({masters[7].arready , masters[6].arready ,masters[5].arready,masters[4].arready , masters[3].arready ,masters[2].arready , masters[1].arready ,masters[0].arready}),  // input wire [2 : 0] m_axi_arready
  .m_axi_rdata              ({masters[7].rdata   , masters[6].rdata   ,masters[5].rdata  ,masters[4].rdata   , masters[3].rdata   ,masters[2].rdata   , masters[1].rdata   ,masters[0].rdata  }),      // input wire [95 : 0] m_axi_rdata
  .m_axi_rresp              ({masters[7].rresp   , masters[6].rresp   ,masters[5].rresp  ,masters[4].rresp   , masters[3].rresp   ,masters[2].rresp   , masters[1].rresp   ,masters[0].rresp  }),      // input wire [5 : 0] m_axi_rresp
  .m_axi_rvalid             ({masters[7].rvalid  , masters[6].rvalid  ,masters[5].rvalid ,masters[4].rvalid  , masters[3].rvalid  ,masters[2].rvalid  , masters[1].rvalid  ,masters[0].rvalid }),    // input wire [2 : 0] m_axi_rvalid
  .m_axi_rready             ({masters[7].rready  , masters[6].rready  ,masters[5].rready ,masters[4].rready  , masters[3].rready  ,masters[2].rready  , masters[1].rready  ,masters[0].rready })    // output wire [2 : 0] m_axi_rready
);

endmodule

